Items where Author is "Padhy, Binayak"
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Murty, M. N. and Nayak, S. S. and Padhy, Binayak (2022) Study on Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier. In: Novel Perspectives of Engineering Research Vol. 7. B P International, pp. 110-116. ISBN 978-93-5547-514-5