Study on Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier

This paper presents a bit-level systolic architecture for a matrix-matrix multiplier based on the proposed algorithm for both positive and negative multiplications. In many real-time systems and digital image processing applications, highly efficient arithmetic operations are required to attain the requisite performance. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial - parallel multiplier, which can perform both positive and negative multiplications, is presented. Baugh-Wooley algorithm necessitates complementation of last bit of each partial product except the last partial product in which all but the last bit are complemented. In the proposed algorithm all bits of the last partial product are complemented. This modification results in considerable reduction in hardware compared to Baugh-Wooley multiplier. This multiplier can be used for implementation of discrete orthogonal transforms, which are used in many applications, including image and signal processing. This paper presents a 2D bit-level systolic architecture for a matrix-matrix multiplier. A comparison with similar structures has shown that the proposed structure performs better. It is concluded that, the structure requires less area and time complexity when compared with some existing structures. Due to simplicity, regularity and modularity, the proposed systolic architecture is suitable for VLSI signal processing applications.